The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Referring now to FIG. 1, a hard disk drive (HDD) system is shown. The HDD system 10 includes a hard disk assembly (HDA) 12 and a HDD printed circuit board (PCB) 14. The HDA 12 includes one or more circular platters (i.e. disks) 16, which have magnetic surfaces that are used to store data magnetically. The disks 16 are arranged in a stack, and the stack is rotated by a spindle motor 18. At least one read and write head (hereinafter, “head”) 20 reads data from and writes data on the magnetic surfaces of the disks 16.
The head 20 includes a write head, such as an inductor, that generates a magnetic field and a read head, such as a magneto-resistive (MR) element, that senses the magnetic field on the disks 16. The head 20 is mounted at a distal end of an actuator arm 22. An actuator, such as a voice coil motor (VCM) 24, moves the actuator arm 22 relative to the disks 16.
The HDA 12 includes a preamplifier 26 that amplifies signals received from and sent to the head 20. The preamplifier 26 generates a write current that flows through the write head of the head 20 when writing data. The write current is used to produce a magnetic field on the magnetic surfaces of the disks 16. Magnetic surfaces of the disks 16 induce low-level analog signals in the read head of the head 20 during reading of the disks 16. The preamplifier 26 amplifies the low-level analog signals and outputs amplified analog signals to a read/write channel module 28.
The HDD PCB 14 includes the read/write channel module 28, a hard disk controller (HDC) 30, a processor 32, a spindle/VCM driver module 34, volatile memory 36, nonvolatile memory 38, and an input/output (I/O) interface 40. The read/write channel module 28 synchronizes a phase of write clock signals with the data islands on the disks 16.
During write operations, the read/write channel module 28 may encode the data to increase reliability by using error-correcting codes (ECC) such as run length limited (RLL) code, Reed-Solomon code, etc. The read/write channel module 28 then transmits the encoded data to the preamplifier 26. During read operations, the read/write channel module 28 receives analog signals from the preamplifier 26. The read/write channel module 28 converts the analog signals into digital signals, which are decoded to recover the original data.
The HDC module 30 controls operation of the HDD system 10. For example, the HDC module 30 generates commands that control the speed of the spindle motor 18 and the movement of the actuator arm 22. The spindle/VCM driver module 34 implements the commands and generates control signals that control the speed of the spindle motor 18 and the positioning of the actuator arm 22. Additionally, the HDC module 30 communicates with an external device (not shown), such as a host adapter within a host device 41, via the I/O interface 40. The HDC module 30 may receive data to be stored from the external device, and may transmit retrieved data to the external device.
The processor 32 processes data, including encoding, decoding, filtering, and/or formatting. Additionally, the processor 32 processes servo or positioning information to position the head 20 over the disks 16 during read/write operations. Servo, which is stored on the disks 16, ensures that data is written to and read from correct locations on the disks 16.
Referring now to FIG. 2, the hard disk drive system 10 stores data on magnetic media in concentric tracks, which are divided into sectors as shown in FIG. 2. When reading the data, the read head flies over the disk and senses a magnetic field stored on the disk.
Referring now to FIG. 3, a typical receiver 90 is shown. The receiver 90 includes an analog front end (AFE) module 100, an equalizer module 104, a detector module 108 and a back end module 112. A continuous-time signal is read from the disk and is processed by the AFE module 100. The AFE module 100 conditions and samples the read-back continuous time signal and outputs a discrete-time signal. The equalizer module 104 receives an output of the AFE module 100 and performs equalization to a pre-determined target. A detector module 108 receives an output of the equalizer module and decodes data. For example only, the detector module 108 may include a sequence detector such as a Viterbi detector. An output of the detector module 108 is used to drive the equalizer module 104 and adaptation of the AFE module 100. Components of the receiver 90 up to and including the detector module 108 are identified in FIG. 3 as front end section 114 and components after the detector module 108 are identified in FIG. 3 as back end section 116.
A user data portion of the output of the equalizer module 104 is further processed by the back end module 112. The back end module 112 performs more sophisticated detection and decoding for the purpose of error correction. The back end module 112 typically includes a nonlinear detector, such as a nonlinear Viterbi detector (NLV).
The AFE module 100 typically performs automatic gain control (AGC) to adjust gain. The equalizer module 104 is also typically adaptive. Adaptation in the AFE module 100 and the equalizer module 104 typically use minimum mean square error (MMSE) criteria. Typically, an amplitude of the output of the equalizer module 104 changes with a single-to-noise ratio (SNR) of the system.
Channel SNR can change from one sector to another sector due to variations in the signal or in the noise. For instance, the SNR changes with read head fly height. The SNR also changes with the amount of inter-track interference (ITI). While the AGC in the AFE module 100 and the equalizer module 104 are optimal or near optimal for the detector module 108, the output of the equalizer module 104 may not be the optimal for the back end section 116.
Referring to FIGs. 2 and 4A, for each data sector, preamble (PRE), syncmark (SM), user data (USERDATA) and post-amble (POST) fields are written on the disk. Two sectors written on two neighboring tracks identified as track n and track n+1 are shown. Typically, sectors on adjacent tracks are closely aligned. As the recording density increases, the distance between two neighboring tracks decreases. When readingtrack n, the read head will also pick up a signal from one or more neighboring tracks, for example track n+1. This phenomenon is called inter-track interference (ITI). The overall read-back signal is the weighted sum of track n and track n+1 as set forth below:rn=(1−α)yn+αyn−1 where rn is the read-back signal, yn is the signal from track n, yn+1 is the signal from track n+1, and α is an off-track percentage factor.
Referring now to FIG. 4B, a typical receiver 120 with ITI cancellation is shown. The ITI cancellation may be applied as a post processing step. The receiver 120 includes an analog front end (AFE) module 122, an equalizer module 124, a detector module 128, an ITI cancellation module 130 and a back end module 132. A front end section 134 includes the AFE module 122, the equalizer module 124, and the detector module 128. A post processing section 136 includes the ITI cancellation module 130. A back end section 138 includes the back end module 132. The ITI cancellation module 130 treats ITI as noise introduced in the front end section 136.